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NCC Circuit Description

This description refers to the Issue 18 and later NCC Mk1 series controllers.
Circuit Diagram

The NCC Mk 2 and the VTX are similar: main additions on these are an adjustable Reverse Acceleration Threshold (a preset on the IC2d, pin 8) and

Power Supply

The power supply is a 30mA current source feeding a 9v1 zener diode, D16.

Tr7 senses the current flowing through the 22R resistor and adjusts the base of Tr6 so that 30mA flows in Tr6. The zener, with parallel 47µ capacitor (C17), is shown near Tr2.

This arrangement has several benefits:

  • It will tolerate a wide input voltage, from about 10v to as much as dissipation and voltage rating in Tr6 will allow.
  • It is generally fail-safe: zener diodes, if overloaded, tend to fail short-circuit acting as crowbar and restricting further damage.


Ignition and ignition pump

The current source is turned on or off by applying base current. When a voltage is applied to the ignition input, Tr3 is turned on and applies base current to Tr6. Tr3’s emitter current also turns on Tr2: see below under Ramp Clamp.

When ignition is removed, Tr3 turns off (as does Tr2) removing this input from the current source. However, if the controller is still switching at the time the ignition is turned off, it is held on by the charge pump consisting of a 100n capacitor C8 from the motor – output feeding 2 diodes and a 4K7 resistor to Tr6’s base. Only when the output stops switching can the ignition finally turn off, delayed by the discharge of C6.

If the MOSFETs are fully on (i.e. not switching) when the ignition signal is removed, the ignition stays on because of C6 but the ramp clamp is activated, so the speed starts to reduce. This causes the MOSFETS to start switching. For this to work properly, the gain must be st so that ful input from the pot only just causes the speed to reach full, and not go into ‘overdrive’.


Ramp Clamp

Tr25 when turned on, clamps the output of IC1a to 0v. IC1a is an open collector LM339 section, so this clamping to 0v overrides its output. When Tr25 turns on therefore the output of the ramp stage will slew to zero speed.

Tr25 is turned on by one of the following conditions:

  • Ignition is turned off.
    When Tr3 is on, so too is Tr2. But when Tr2 is off, current flows through its 10K collector resistor and D15 into the base of Tr25, turning it on. So when the ignition is turned off at speed, the controller ramps down to zero and only then does the ignition pump turn the ignition off.If there is a fault in the output, e.g. the MOSFETs have failed, then the output will not be switching and the ignition will not be held on by the pump, so will deactivate immediately. This, incidentally, is why the gain should be set correctly: it is is set too high, the demand speed will be well over that required for full speed, so there will be a delay between the start of the ramp down and the MOSFETs starting to switch. In this case, the ignition will react as for an output fault and will immediately deactivate.
  • Input direction is different from actual direction.
    D17 and D18 with D19 and D20 and the two 100K resistors form a logic gate whose output is high if selected direction (input and output of IC2c) is different from the actual direction latched in the direction latch.


PWM oscillator

IC1b with D10, D11, Cr and associated resistors form a sawtooth oscillator which gives a sawtooth between about 0.5v and 2.8v.

On pin 5 of the IC, 10K and 22K resistors divide the 9.1v supply rail to give 2.8 volts.

The 330K resistor charges up C4 and, as it does, pin 4 of IC1b rises.

When pin 4 is higher than pin 5, IC1b pin 2 conducts, pulling the output low.

Now D10 and D11 will both conduct. Both inputs are pulled low but (once C4 has fully discharged) the current through D10 will always be more than (about 15 times) that through D11 since D10’s current is defined by the 330K and D10’s by the 22K. So pin 4 must fall below pin5 and the comparator will again switch so its output is off (high).



If you are new to PWM, there is an article for beginners on how PWM works. The sawtooth (generated by ICIb) on C4 is fed into pin 8 of IC1d. Into pin 9 is fed the demand speed.


Loside driver

Tr 18 and Tr19 are the low side drivers. C11, as far as the low side drivers are concerned, it between the bases and earth, so it tends to slow up the rise time became IC1d is off at this time and the capacitor is charging via the 1K0 pull up resistor. However the charging current flows into Tr17’s base, causing it to switch earlier.

These driver transistors are capable of feeding significant current to the MOSFETs to cause them to switch at an adequate rate.

D12 has no function in normal use: only under fault conditions does it operate, so it, together with the 10R gate resistors and the driver transistors (especially the PNP) must be checked and replaced if required whenever a MOSFET fails.


Loside Current limit

Full operation of this current limit circuit is available to 4QD-TEC members but it uses the MOSFET Rds(on) sensing described in MOSFET current sensing. Since it rarely goes wrong, a full description here is academic, but is available to 4QD-TEC members.

When current limit engages, IC1c conducts and reduces the demand speed input to the modulator, thus reducing the output current.

During service, it is adequate to simply test that the current limit is working: a check of levels is never needed. The method of testing is given in the 4QD public service area.


Hiside driver

This uses a bootstrap voltage pump do deliver a gate voltage 9v higher than the supply. When MF1 is conducting, C 10 charges to nearly the full battery supply voltage via D6 (and the 22R) and MF1. When MF1 is conducting, its gate voltage is high, so Tr17 is conducting and there is some current also flowing through the 47K resistor but the bases of the hiside drivers, Tr 12 and Tr13, are pulled to within less than 1v of the battery – line so MF2 cannot conduct.

When the base drive to MF1 starts to fall, Tr17’s base drive is removed, speeded up by the 470p capacitor, and Tr17’s collector voltage rises. The 47K now pulls the bases of TR12 and Tr13 high, but the voltage rise is limited to 9v by D9. Tr12 applies enough charge (derived from C10) to the gates of MF2 MOSFET(s) to turn them on.


Hiside Current limit and supply overvoltage clamp

A full description of how this works is available to 4QD-TEC members: It is the circuitry comprising Tr5 and Tr4 with associated resistors. It rarely goes wrong, so a full description is not indicated here.

Tr5 turns on is there is more than 1.33 Vbe’s (but less than 2) present across MF2 and injects a signal into the PWM modulator: the assumption is that the excess MF2 voltage is caused by too much regenerated current, so we have to reduce regen i.e. we need to accelerate.

Leakage or voltage breakdown in Tr5 can cause the limit to engage when it should not. This transistor must withstand the full supply voltage.

D4 is the overvoltage clamp. The assumption is that excess voltage on the supply is caused by the battery having fallen off the machine and the excess voltage is caused by the controller regenerating into a non-existent battery. Since it is the battery which does the braking and not the controller, the controller cannot brake and must protect itself by reducing the deceleration that is causing the regenerated overvoltage.

Clearly – this will also engage if the controller is being used from a mains power supply that cannot accept reverse current into its output. It may also occur if for instance, the user lives at the top of a hill and start off down hill with fully charged batteries: this only occurs on 48v controllers where the overvoltage clamp is 56v.


Input buffer

Input form the 10K pot, is to pin E of the 6 way connector. The gain preset simply adjusts the amount of the pot voltage seen by the controller.

IC1 buffers this voltage and feeds it to the ramps.


Pot Fault


Tr1 is the pot fault detector. It is turned on by the current through the pot. If the pot resistance is too high, or a wrong wire has broken, Tr14 will not conduct. IC1 is part of an LM339 which has no internal pullup: if Tr1 does not conduct, nothing else can pull pin 1 high, so the ramp circuit can get no input and remains at zero speed.



The ramp capacitor, C3, charges via D4 and the accel preset and discharges via D3 and the decel pot.

If the voltage across the accel preset rises enough, Tr21 turns on and robs the charging current through D4 so the maximum charging current through the accel preset cannot exceed this value – which is dependant on the adjustment of the accel preset. This limits the maximum charge rate (hence dV/dt) of C3.

A similar mechanism causes Tr22 to limit the deceleration ramp.


Ramp Follower and Expansion connector

Tr14 is present to avoid the modulator and other bits loading the ramp capacitor. The ramp follower feeds

  • Modulator, IC1d, via a 10K resistor which is present to define an impedance for the half speed reverse switch, Tr26. When Tr26 is on, its collector resistor divided the follower’s output by two.
  • Current limiter. IC1c, see above.
  • Expansion connector. Used for ‘dual heading’ and for adding extras such as a tacho generator feedback.
  • Demand speed detector, IC2d


Demand speed detector

The ramp output is fed to IC2d, the Demand speed detector. Pin 8 is held at about 200mV, derived from D21. When the demand speed is above this, pin 14 goes high operating the parking brake and latching the current direction into the direction latch (IC2a and IC2b).



The direction switch applies a high on pin C. If this high is above about 5v (defined by the Vbe of Tr10 and its two base resistors) then Tr10 turns on. If Tr10 is off, its collector resistor (10K) pills pin 10 of IC2c high – forward has been selected. If Tr10 is conducting (reverse selected) pin 10 is pulled low. Pin 11 of IC2 is held at about 4.5v by the divider chain.

IC2 is therefore an inverter. It drives the direction latch. Its input and output also drive the 100K resistors into the diode bridge, D17, D18, D19 and D20. This arrangement gives a output is the selected direction and the latched direction are different: see Ramp Clamp, above.


Direction Latch

IC2a and IC2b is, essentially, a 3 state ‘bistable’ latch. When the output of the demand speed detector, IC2d, is low, pins 5 and 7 of the latch are low so both outputs (pins 1 and 2) of the direction latch are low and both relays are off.

As soon as demand speed is detected by IC2d, pins 5 and 7 are pulled up to about 6.2 volts (defined by the resistor chain) and the latch goes into one or other stable state: the two stable states are with pin 1 high OR with pin 2 high. It is not possible for both to be high simultaneously. Which output goes high first depends on the state of the reverse line, pin 13 of IC2c.

Pin 6 of the latch is at 4.5v when there is no demand speed and at 9.1v when there is demand speed.

Pin 4, in the absence of demand speed, is at 3.7v or 5.4v, depending on the state of IC2c pin 13. Thus, when pin 7 rises as demand speed is detected, the latch will fall into one or other state depending on whether pin 4 is above or below pin 6 in voltage.

This is a remarkably predictable and reliable latch: the only problem is when C21 or C22 is absent when noise transients, as the latch operates, can cause problems.


Relay Drivers

Since the reversing latch outputs have 10K pullup resistors (to minimise internal supply current), we require a high impedance drive to the relay drivers to avoid unpredictable loading, so complementary darlington stages are used to drive the relays. Tr 27 and Tr28 drive the reverse relay and Tr29 and 30 drive the forward relay.


Parking Brake Driver

Similar to the relay drivers, this uses a PNP power transistor as it has to switch up to 1 amp.

The drive is fed via D22 into C19: C19 charges up quickly through D22 and the 10K pullup but discharges slowly, delaying the release of the solenoid (i.e. that application of braking power) for a fraction of a second.


Dual Ramp reversing

If you have followed the foregoing description, you should now understand how dual ramp reversing works.

Consider the controller going at speed, forward.

  1. Input pin C is low.
  2. Tr10 is off.
  3. IC2c pin 10 is high
  4. IC2c pin 13 is low
  5. As there is demand input, pin 9 of IC2d will be high and pin 14 will be high.
  6. The inputs pins 5 and 7 to the latch IC2a and IC2b will be high so the latch will be in a stable state with pin 2 high, pin 1 low.
  7. The forward relay will be closed, the reverse open. D20 will be reversed biased: the 100K to pin 13 cannot forward bias it as pin 13 is low.
  8. D19 will be conducting, so there is no voltage on D17.
  9. Now the reverse input is applied: input pin C goes high.
  10. Tr10 conducts
  11. IC2c pin 10 goes low
  12. IC2c pin 13 goes high
  13. There is still demand speed. The latch is still latched.
  14. The 100K from pin 13 now feeds current to D18 (D20 ‘s positive is still high)
  15. D18 conducts and feeds voltage into the base of Tr25, which clamps the demand speed (input to the ramp circuit) low.
  16. The circuit ramps down to zero speed. Specifically until IC22 pin 9 falls to the voltage on pin 8 and pin 14 goes low.
  17. At zero speed, pin 9 of IC2d goes low: pin 14 follows. There is a slight delay here caused by C20. In speed critical applications it is permissible to remove C20.
  18. The ‘latch’ line, pins 5 and 7 goes low, forcing both outputs (pins 1 and 2) low. Both relays off.
  19. D20 now conducts, clamping the junction of D18 and D20 low, so D18 can no longer feed a signal to the ramp clamp Tr25.
  20. The demand speed, pre ramp, returns to that set by the throttle device and the controller starts ramping up to speed.
  21. As soon IC2d detects a demand speed, its output goes high and the latch goes to s stable state determined by the voltage of pin 4.
  22. As we have now reverse selected, pin 13 of IC2c is high so pin 4 will be at 5.4v and IC2a will turn on, latching in the reverse direction.